AFBR-S50 API Reference Manual  v1.6.5
AFBR-S50 Time-of-Flight Sensor SDK for Embedded Software
argus_irq.h
Go to the documentation of this file.
1 /*************************************************************************/
37 #ifndef ARGUS_IRQ_H
38 #define ARGUS_IRQ_H
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 /*!***************************************************************************
44  * @defgroup argus_irq IRQ: Global Interrupt Control Layer
45  * @ingroup argus_hal
46  *
47  * @brief Global Interrupt Control Layer
48  *
49  * @details This module provides functionality to globally enable/disable
50  * interrupts in a nested way.
51  *
52  * Here is a simple example implementation using the CMSIS functions
53  * "__enable_irq()" and "__disable_irq()". An integer counter is
54  * used to achieve nested interrupt disabling:
55  *
56  * @code
57  *
58  * // Global lock level counter value.
59  * static volatile int g_irq_lock_ct;
60  *
61  * // Global unlock all interrupts using CMSIS function "__enable_irq()".
62  * void IRQ_UNLOCK(void)
63  * {
64  * assert(g_irq_lock_ct > 0);
65  * if (--g_irq_lock_ct <= 0)
66  * {
67  * g_irq_lock_ct = 0;
68  * __enable_irq();
69  * }
70  * }
71  *
72  * // Global lock all interrupts using CMSIS function "__disable_irq()".
73  * void IRQ_LOCK(void)
74  * {
75  * __disable_irq();
76  * g_irq_lock_ct++;
77  * }
78  *
79  * @endcode
80  *
81  * @note The IRQ locking mechanism is used to create atomic sections
82  * (within the scope of the AFBR-S50 API) that are very few processor
83  * instruction only. It does NOT lock interrupts for considerable
84  * amounts of time.
85  *
86  * @note The IRQ_LOCK might get called multiple times. Therefore, the
87  * API expects that the IRQ_UNLOCK must be called as many times as
88  * the IRQ_LOCK was called before the interrupts are enabled.
89  *
90  * @note The interrupts utilized by the AFBR-S50 API can be interrupted
91  * by other, higher prioritized interrupts, e.g. some system
92  * critical interrupts. In this case, the IRQ_LOCK/IRQ_UNLOCK
93  * mechanism can be implemented such that only the interrupts
94  * required for the AFBR-S50 API are locked. The above example is
95  * dedicated to a ARM Corex-M0 architecture, where interrupts
96  * can only disabled at a global scope. Other architectures like
97  * ARM Cortex-M4 allow selective disabling of interrupts.
98  *
99  * @addtogroup argus_irq
100  * @{
101  *****************************************************************************/
102 
103 /*!***************************************************************************
104  * @brief Enable IRQ Interrupts
105  *
106  * @details Enables IRQ interrupts and enters an atomic or critical section.
107  *
108  * @note The IRQ_LOCK might get called multiple times. Therefore, the
109  * API expects that the IRQ_UNLOCK must be called as many times as
110  * the IRQ_LOCK was called before the interrupts are enabled.
111  *****************************************************************************/
112 void IRQ_UNLOCK(void);
113 
114 /*!***************************************************************************
115  * @brief Disable IRQ Interrupts
116  *
117  * @details Disables IRQ interrupts and leaves the atomic or critical section.
118  *
119  * @note The IRQ_LOCK might get called multiple times. Therefore, the
120  * API expects that the IRQ_UNLOCK must be called as many times as
121  * the IRQ_LOCK was called before the interrupts are enabled.
122  *****************************************************************************/
123 void IRQ_LOCK(void);
124 
126 #ifdef __cplusplus
127 } // extern "C"
128 #endif
129 #endif // ARGUS_IRQ_H
IRQ_LOCK
void IRQ_LOCK(void)
Disable IRQ Interrupts.
IRQ_UNLOCK
void IRQ_UNLOCK(void)
Enable IRQ Interrupts.