Global Interrupt Control Layer.
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void | IRQ_UNLOCK (void) |
| Enable IRQ Interrupts.
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void | IRQ_LOCK (void) |
| Disable IRQ Interrupts.
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Global Interrupt Control Layer.
This module provides functionality to globally enable/disable interrupts in a nested way.
Here is a simple example implementation using the CMSIS functions "__enable_irq()" and "__disable_irq()". An integer counter is used to achieve nested interrupt disabling:
static volatile int g_irq_lock_ct;
{
assert(g_irq_lock_ct > 0);
if (--g_irq_lock_ct <= 0)
{
g_irq_lock_ct = 0;
__enable_irq();
}
}
{
__disable_irq();
g_irq_lock_ct++;
}
void IRQ_UNLOCK(void)
Enable IRQ Interrupts.
void IRQ_LOCK(void)
Disable IRQ Interrupts.
- Note
- The IRQ locking mechanism is used to create atomic sections (within the scope of the AFBR-S50 API) that are very few processor instruction only. It does NOT lock interrupts for considerable amounts of time.
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The IRQ_LOCK might get called multiple times. Therefore, the API expects that the IRQ_UNLOCK must be called as many times as the IRQ_LOCK was called before the interrupts are enabled.
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The interrupts utilized by the AFBR-S50 API can be interrupted by other, higher prioritized interrupts, e.g. some system critical interrupts. In this case, the IRQ_LOCK/IRQ_UNLOCK mechanism can be implemented such that only the interrupts required for the AFBR-S50 API are locked. The above example is dedicated to a ARM Corex-M0 architecture, where interrupts can only disabled at a global scope. Other architectures like ARM Cortex-M4 allow selective disabling of interrupts.
◆ IRQ_LOCK()
◆ IRQ_UNLOCK()